1. Field of the Invention
The invention generally relates to a field effect transistor (FET) structure and, more particularly to a FET structure that incorporates a multi-layer low-K dielectric spacer to suppress capacitance coupling between the gate and the source and drain extensions.
2. Description of the Related Art
The metal-oxide-semiconductor field-effect transistor (MOSFET) is the building block of very large scale integrated (VLSI) circuits in microprocessors and dynamic memories. MOSFETs are four-terminal devices with the terminals designated as the gate conductor, the source and drain regions and the channel. The channel and source and drain regions lie in a substrate on which the gate conductor is positioned. Generally, the channel lies directly beneath the gate conductor with the source and drain regions on either side of the channel. While most of the source and drain regions do not lie beneath the gate, small portions of the source and drain regions referred to as extensions may overlap the gate to enhance MOSFET performance by achieving immunity to short-channel effects. These source and drain extensions may be lightly doped and not as deep as compared to the rest of the source and drain regions. The gate conductor is usually made of a metal or a heavily doped polysilicon and is separated from the channel and the source and drain extensions by a thin oxide film (i.e., gate oxide), such as a silicon dioxide (SiO2) film. Since the gate conductor is electrically insulated from the channel, the channel is capacitively coupled to the gate via the electric field in the gate oxide. The switching speed of the MOSFET is mainly determined by the device drive current and the intrinsic capacitance between the channel and the gate conductor. However, in MOSFET structures in which the gate oxide also overlaps the source and drain extensions, a significant parasitic capacitance is created between the gate conductor and the source and drain extensions. The parasitic capacitance consists of three components: direct overlap capacitance, outer fringe capacitance and inner fringe capacitance. This parasitic capacitance can significantly reduce the MOSFET switching speed and, thereby, can degrade the performance of the MOSFET in alternating current (AC) applications. The invention described below addresses the issue of this parasitic overlap capacitance.